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PACNLT101
Non-Linear High Speed Termination IC
Features
* 16 channel, dual rail clamping action in a single package * Provides bus termination independent of line impedance or loading conditions * Uses CAMD's patented EZtermTM technology * 24-pin QSOP package saves board space and eases layout in space critical areas. * One IC replaces and outperforms up to 32 discrete components. * Enable pin included
Application
* High speed, low voltage buses
Product Description
CAMD's non-linear termination IC is specifically designed to minimize overshoot/undershoot disturbances caused by impedance mismatch reflections and noise on high-speed transmission lines. Reflections on high-speed data lines lead to voltage overshoot and undershoot disturbances, which may result in data loss or improper system operation. Resistive terminations, when used to terminate these highspeed data lines, increase power consumption and degrade output levels, resulting in reduced noise immunity. Clamping-type termination is the best overall solution for applications in which these may be considerations. This highly integrated non-linear termination IC provides very effective termination performance for high-speed data lines under variable loading conditions. The device supports up to 16 terminated lines per package - each of which are clamped to both ground and power supply rail. A typical application may use 4 devices to replace (and outperform) 64 conventional Schottky diode pairs; thus providing significant reductions in component and assembly costs, improvements in manufacturing efficiency and reliability, and savings in allocated board area for space-critical designs.
Pin Configuration
Top View NLT#1 NLT#2 NLT#3 GND NLT#4 NLT#5 NLT#6 NLT#7 GND NLT#8 NLT#9 NLT#10 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VDD VDD NLT#16 GND NLT#15 NLT#14 NLT#13 NLT#12 GND NLT#11 Enable VDD
PACNLT101 24-Pin QSOP
Standard Part Ordering Information
Package Pin 24 Style QSOP Ordering Part Number Tape & Reel Part Marking PACNLT101Q PACNLT101Q
(c)2001 California Micro Devices Corp. All rights reserved. EZtermTM is a trademark of California Micro Devices
C1601100
215 Topaz Street, Milpitas, California 95035
3/8/2001
Tel: (408) 263-3214
Fax: (408) 263-7846
www.calmicro.com
1
PACNLT101
Absolute Maximum Ratings
Parameter Maximum DC Voltage on any pin Minimum DC Voltage on any pin Continuous current per channel Operating Temperature (Ambient) Storage Temperature (Ambient) Power Dissipation @ T = 25C Rating 3.6 -0.5 72 -40 to 85 -65 to 150 0.9 Unit V V mA
C C
W
Operating Characteristics - VDD = 3.3V, Enable = 3.3V, Temperature = -40C to 85C
Operating Characteristics -- 3.3V
Parameter Signal Voltage VDD current Enable pin (pin 14) current Input Capacitance* ESD protection Response Time
*These parameters are guaranteed by design and characterization.
Conditions above VDD @ I = 50mA below GND @ I = -50mA all Channels floating all Channels floating Signal voltage = VDD Signal voltage = VDD/2 MIL-STD-883, method 3015*
MIN
TYP 610 510 85 10 3.4 3.0
MAX 850 750 150 15
UNIT mV mV mA mA pF pF kV
4 400
ps
Operating Characteristics - VDD = 2V, Enable = 2V, Temperature = -40C to 85C
Operating Characteristics -- 2.0V
Parameter Signal Voltage VDD current Enable pin (pin 14) current Input Capacitance* ESD protection Response Time
*These parameters are guaranteed by design and characterization.
Conditions above V DD @ I = 20mA below GND @ I = -20mA all Channels floating all Channels floating Signal voltage = VDD Signal voltage = VDD/2 MIL-STD-883, method 3015*
MIN
TYP 390 300 25 3.5 3.5 3.2
MAX 600 500 42 5.5
UNIT mV mV mA mA pF pF kV
4 400
ps
Operating Characteristics - VDD = 2.5V, Enable = 2.5V, Temperature = 27C
Operating Characteristics -- 2.5V
Parameter Signal Voltage VDD current Enable pin current Conditions above V DD @ I = 30mA below GND @ I = -30mA all Channels floating all Channels floating MIN TYP 470 375 50 6 MAX UNIT mV mV mA mA
(c)2001 California Micro Devices Corp. All rights reserved. EZtermTM is a trademark of California Micro Devices
2
215 Topaz Street, Milpitas, California 95035
Tel: (408) 263-3214
Fax: (408) 263-7846
www.calmicro.com
3/8/2001
PACNLT101
50 45 40 35
Current (mA)
30 25 20 15 10 5 0 0 100 200 300 400 500 600 VDD = 3.3V VDD = 2.0V
Voltage above VDD (mV)
Figure 1. DC I-V Curves for VDD = 2V and VDD = 3.3V
Application Information
Figure 2 shows one method of configuring the printed circuit board such that all 16 terminated signals are easily accessible. The decoupling capacitor should be a high-frequency type, 0.1F or larger, and placed as close to the IC as possible. This will minimize the positive overshoot voltage and also reduce EMI emissions. It should be noted that for optimum performance the PACNLT101 termination should be located as physically close to the receiving IC input as is possible.
1 2 3
24 23 22 21 20 19 18 17 16 15 14 13
VDD 0.1F GND
GND
4 5
16 Terminated Signals GND
6 7 8 9 10 11 12
PACNLT101 GND via
Figure 2. Printed Circuit Board with Accessible Configuration for 16 Terminated Signals
(c)2001 California Micro Devices Corp. All rights reserved. EZtermTM is a trademark of California Micro Devices
215 Topaz Street, Milpitas, California 95035
3/8/2001
Tel: (408) 263-3214
Fax: (408) 263-7846
www.calmicro.com
3
PACNLT101
VCC Non-Linear Clamp Termination
Driver 7SZ04
Transmission Line
Receiver 74AC244
GND
Figure 3. Example Circuit: Single-Driver/Single Receiver
Tek
5GS/s
136 Acqs : 2.50V @: 0V C1 Rise 1.14ns C1 Fall 1ns C1 Max 3.30V C1 Min -1.20V
1V
M 10ns Ch1
1.24V
Figure 4. 74AC244 Termination Only
Tek
5GS/s
44 Acqs : 2.50V @: 0V C1 Rise 1.18ns C1 Fall 1ns C1 Max 2.82V C1 Min -500mV
1V
M 10ns Ch1
1.24 V
Figure 5. With PACNLT101 Termination
(c)2001 California Micro Devices Corp. All rights reserved. EZtermTM is a trademark of California Micro Devices
4
215 Topaz Street, Milpitas, California 95035
Tel: (408) 263-3214
Fax: (408) 263-7846
www.calmicro.com
3/8/2001
PACNLT101
Enable pin
In normal use the Enable pin is connected to VDD. If the Enable pin is set to 0V or disconnected (high impedance), then the PACNLT101 will be disabled. The supply current will drop to almost zero and the clamping performance will be worsened. The Enable pin can also be used to vary the supply current and clamping voltage. As the current into the Enable pin is increased the supply current will increase and the clamping voltage will be reduced. The minimum clamping voltage will occur when the Enable pin voltage equals the supply voltage. (The Enable pin voltage cannot exceed the supply voltage.) Users who cannot tolerate the supply current quoted in the Operating Characteristics can connect a resistor in series with the Enable pin to reduce the supply current, at the cost of increasing the clamping voltage. See Figure 6. The controller IC sets the powerdown pin to 0V to powerdown the PACNLT101, and sets the powerdown pin to VDD to power up the PACNLT101. The system designer can vary the value of R1 to optimize the tradeoff between power consumption and clamping voltage. See Figure 7, 8, 9, and 10.
PACNLT101 R1 Enable
Controller Powerdown
Figure 6. Resistor In Series with the Enable Pin
100 90 80 70
IDD (mA) Clamping Voltage above VDD for 50mA (mV)
800 750 700 650 600 550 500
60 50 40 30 20 10 0 0 100 220 470 1000 2200 Value of External Resistor R1 ()
0
100
220
470
1000
2200
Value of External Resistor R1 ()
Figure 7. IDD vs R1 @ VDD = 3.3V
Figure 8. Clamping Voltage vs R1 @ VDD = 3.3V
30
Clamping Voltage above VDD for 20mA (mV)
650 600 550 500 450 400 350 300 0 100 220 470 1000 2200 4700 10000 100000
25 20
IDD (mA)
15 10 5 0 0 100 220 470 1000 2200 4700 10000 100000 Value of External Resistor R1 ()
Value of External Resistor R1 ()
Figure 9. IDD vs R1 @ VDD = 2V
(c)2001 California Micro Devices Corp. All rights reserved. EZtermTM is a trademark of California Micro Devices
Figure 10. Clamping Voltage vs R1 @ VDD = 2V
Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com
215 Topaz Street, Milpitas, California 95035
3/8/2001
5

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